The present invention relates generally to Phase-Lock Loop (PLL) circuits and more specifically to a charge pump circuit injecting low noise and low charge into particular PLL circuits.
FIG. 3 is a block diagram of a conventional PLL circuit 100. The PLL circuit 100 of the prior art uses a charge pump 102 in conjunction with a low pass filter (LPF) 104 to establish a control voltage for a voltage-controlled oscillator (VCO) 106. One purpose of a PLL circuit is to produce an output clock signal (CLK OUT) having a frequency proportional to an input signal (SIG IN). A phase/frequency detector (PFD) 108 compares the input signal and a feedback signal from the VCO 106 to determine any differences in phase or frequency between the two signals. The PFD 108 controls the operation of the charge pump 102 through assertions and negations of two control signals, an UP signal and a DOWN signal. The charge pump 102 responds to the UP and DOWN signals in different ways, depending upon particular implementations of the PLL circuit 100. In one instance, the charge pump 102 responds to an assertion of the UP signal to provide more voltage to the LPF 104 which causes a greater voltage at the VCO 106 input. For certain implementations, the VCO 106 responds to a greater voltage at its input by increasing the output clock's frequency to a new value determined by the magnitude of the voltage at the VCO 106 input. If this new value has a frequency greater than the input signal, the PFD 108 detects a frequency difference between the feedback signal and the input signal, causing it to assert the DOWN signal to the charge pump 102. The charge pump 102 responds to the DOWN signal assertion by causing the voltage level at the VCO 106 input to decrease. The decreased voltage level decreases the output signal's frequency. The PFD 108 continually compares the input signal with the feedback signal and periodically asserts UP and DOWN depending upon the comparison results.
One difficulty with the charge pumps 102 of the prior art relate to precise control over the magnitude of the charge which it injects into the LPF 104. The charge pump 102 includes one or more driver circuits which the UP and DOWN signals control. Many factors may affect the imprecise control over the injected charge. These factors include noise coupled to driver circuits of the charge pump or switching times for the driver circuit elements. If the driver circuits are slow to respond to the UP and DOWN signals, or if the driver circuits have a minimum period for which they must be active which is greater than assertion periods for the UP and DOWN signals, then the imprecise control introduces phase errors in the PLL circuit 100. The noise level fluctuations superimposed over supply and control voltages for the driver circuits will also introduce phase jitters. The charge pump can introduce phase errors or phase jitter if its driver circuit's activation control voltage varies. Variation in the activation voltage can depend upon supply line voltages. One example of a circuit having variable activating voltages would be a driver circuit controlled by a field effect transistor coupled to a current path of the driver. Phase error results from too much or too little injected charge. Phase jitter, however, results from random phase changes caused by noise.
It is therefore an object of the present invention to provide a charge pump having controllable charge injection and low noise characteristics to reduce phase errors and jitters of the PLL circuit. An additional object of the present invention is to have a charge pump which has a predeterminable activation voltage without control voltage degradation during activation.